Analog IC layout · open PDKs · in the browser

From SPICE netlist to routed analog layout.

AICL Co-pilot builds every device from the PDK, places them with matching and symmetry in mind, routes the nets you leave to it, and checks the result with DRC, LVS and simulation. You stay in control of every cell and every wire.

Try it as a guest Sign in with an invite No install. A guest session needs no account.

One design, four steps

The tour above takes a telescopic OTA through the whole flow on IHP SG13G2. Each step is a page in the editor. Placement and routing run automatically or by hand, and you can mix the two: stop at any point, change things yourself and carry on.

Generate

Netlist in, devices out

Upload a SPICE netlist. aicl builds every transistor, resistor and capacitor from the PDK as a live generator: change fingers or sizes and the device is rebuilt.
Place

Automatic or by hand

A placer lays the devices out for you, keeping differential pairs and current mirrors symmetric. Or place them yourself: move, rotate and mirror any cell, then let the placer tidy up, or re-place with one click.
Route

Automatic or by hand

Draw wires yourself, or sketch a critical net's path and let the router follow it. The router keeps what you drew and routes everything else through the whole hierarchy, with vias from the PDK's rules.
Verify

DRC, LVS, simulation

KLayout DRC and LVS mark each violation on the canvas. ngspice runs your testbench before layout and again on the extracted layout, with the waveforms to compare.

Built for analog work

The editor is a layout editor for a generator. Geometry always comes from the PDK, so what you draw stays correct by construction.

Change the process

Move a design from IHP SG13G2 to SkyWater 130: every device is rebuilt for the new PDK.

Standard cells and abstracts

Import GDS and LEF cells and place several at once next to the generated devices.

Hierarchy

Group cells into modules, edit inside them, and route a module or the whole design.

Pre- and post-layout simulation

Testbenches for amplifiers, comparators, oscillators, LDOs and more drive your ports by role. You get the metrics and the waveforms (AC, noise, transient, operating point); after layout, LVS and parasitic extraction run first and each metric's change is shown.

Sessions on any computer

Your canvases are kept on the server. Close the tab, open the editor on another machine and carry on.

Fast in the browser

The canvas is a Rust and WebAssembly core drawn with WebGL, so large layouts still zoom and pan smoothly.

Or just ask for it

An AI agent works on the open canvas with aicl's own tools. It creates and configures transistors, resistors, capacitors and modules, wires their terminals, places them on the canvas and edits the cells already there. Every change it makes is one undo step, so you can step back through its work.

Uses the model you choose: OpenAI, Anthropic, or any OpenAI-compatible server, including a local one
Builds with the same generators as the editor, so its devices are correct by construction
Shows each tool call it makes, with the result

The agent is in testing and will open to accounts after the test phase.

Create an NMOS differential pair with 4 fingers per device, 2 µm finger width and 0.18 µm length, and a PMOS current-mirror load with 4 fingers of 4 µm. Put the load directly above the pair.

tscell_set_structure_type('pmos_mirror_load', …)

canvas_put_cell(cell='nmos_diff_pair', …)

canvas_set_position(path='pmos_mirror_load', …)

Created and synced on the active canvas: an NMOS differential pair (2 devices, 4 fingers each, 2 µm finger width, 0.18 µm length, matched interdigitated layout) and a PMOS current-mirror load (2 devices, 4 fingers each, 4 µm finger width). The PMOS load is positioned directly above the differential pair with left edges aligned.

Simulated before and after layout

The same ngspice testbench runs on the schematic and on the layout. For the layout run, LVS checks the layout against the netlist first, then the parasitics are extracted. Here a five-transistor OTA on IHP SG13G2, placed and routed automatically: before layout solid, after layout dashed.

Open-loop gain · UGB 18.1 MHz → 17.6 MHz after layout

Five-transistor OTA · IHP SG13G2 · ngspice, typical corner
Metric	Schematic	Layout	Change
Unity-gain bandwidth	18.1 MHz	17.6 MHz	−2.6 %
Phase margin	51.25°	51.57°	+0.32°
DC gain	31.27 dB	31.27 dB	0.0 %
Input noise	257.2 µV_rms	259.3 µV_rms	+0.8 %
Power	16.09 µW	16.09 µW	0.0 %
LVS	netlist vs layout		match
Extraction	34 parasitic capacitors		24.4 fF

One click on the Simulate page: both runs, the checks between them, every metric's change and the waveforms.

Processes

A process is a set of rules aicl reads: layers, devices, design rules, decks and simulation models. The open and mock PDKs come with the editor.

What works on each process today
Process	Kind	Layout	DRC · LVS	Simulation
IHP SG13G2	Open PDK · 130 nm SiGe BiCMOS	Ready	KLayout	Before and after layout
SkyWater SKY130	Open PDK · 130 nm CMOS	Ready	KLayout	Before and after layout
ASAP7	Predictive · 7 nm FinFET	FinFET designs	KLayout	Coming
mock22 · 32 · 45 · 65	Mock · planar, PTM models	Ready	KLayout	Before and after layout
Your PDK	Proprietary	Set up from the PDK's rules, decks and models, on a server of your own. Ask at [email protected].

Your designs stay yours

Private to you

Every session runs in a sandbox of its own, with no network access and no view of other sessions
No other user can see, open or join your designs, and your uploads are kept apart from everyone else's
Sessions are tied to your sign-in: reopen them from any computer, close them when you are done
End a session and the server drops its saved copy; the nightly backups roll over within two weeks

Take them with you

GDS, written with the process's own layer map, ready for your sign-off tools
Canvas files that open again with placement, routes and notes
Design databases saved to a folder on your own computer
Generator scripts: aicl Python that rebuilds the design from its parameters (runs on the aicl backend only; ask at [email protected] for details)
Images as SVG or PNG, for papers and slides

Try it now

The editor is in an early test phase. Anyone can try a small design as a guest. Accounts are by invitation.

Guest

No account, starts at once
Designs up to 15 devices, one canvas
Build, place, route and simulate before layout, on the open and mock PDKs
Your work is deleted four hours after you leave

Continue as a guest

Account

Designs up to 40 devices, three canvases
GDS, LEF and netlist uploads
DRC, LVS and post-layout simulation
Sessions kept and backed up

Ask for an invite at [email protected]